[all-commits] [llvm/llvm-project] 475ce4: RFC: Uniformity Analysis for Irreducible Control Flow

Mon Dec 19 17:52:54 PST 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 475ce4c200ca640f1d6ccd097b167a04f009cb18
      https://github.com/llvm/llvm-project/commit/475ce4c200ca640f1d6ccd097b167a04f009cb18
  Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
  Date:   2022-12-20 (Tue, 20 Dec 2022)

  Changed paths:
    A llvm/docs/ConvergenceAndUniformity.rst
    M llvm/docs/CycleTerminology.rst
    M llvm/docs/Reference.rst
    A llvm/docs/convergence-both-diverged-nested.png
    A llvm/docs/convergence-closed-path.png
    A llvm/docs/convergence-divergent-inside.png
    A llvm/docs/convergence-divergent-outside.png
    A llvm/docs/convergence-natural-loop.png
    M llvm/include/llvm/ADT/GenericCycleInfo.h
    A llvm/include/llvm/ADT/GenericUniformityImpl.h
    A llvm/include/llvm/ADT/GenericUniformityInfo.h
    A llvm/include/llvm/ADT/Uniformity.h
    A llvm/include/llvm/Analysis/UniformityAnalysis.h
    M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
    M llvm/include/llvm/CodeGen/MachinePassRegistry.def
    M llvm/include/llvm/CodeGen/MachineSSAContext.h
    A llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/include/llvm/IR/SSAContext.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/lib/Analysis/CMakeLists.txt
    A llvm/lib/Analysis/UniformityAnalysis.cpp
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
    M llvm/lib/CodeGen/MachineSSAContext.cpp
    A llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
    M llvm/lib/IR/SSAContext.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Passes/PassRegistry.def
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/atomics-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/atomics.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/hidden-diverge.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/irreducible/irreducible-1.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/loads-gmir.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/never-uniform.mir
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/temporal-diverge-gmir.mir
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/always_uniform.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/b42473-r1-crash.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/control-flow-intrinsics.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/hidden_diverge.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/hidden_loopdiverge.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/inline-asm.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/interp_f16.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll
    R llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/branch-outside.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/diverged-entry-basic.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/diverged-entry-headers-nested.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/exit-divergence.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/irreducible-1.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/irreducible-2.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/irreducible/reducible-headers.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/join-at-loop-exit.ll
    A llvm/test/Analysis/DivergenceAnalysis/AMDGPU/join-at-loop-heart.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/llvm.amdgcn.buffer.atomic.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/llvm.amdgcn.image.atomic.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/no-return-blocks.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/phi-undef.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/propagate-loop-live-out.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/temporal_diverge.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/trivial-join-at-loop-exit.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/unreachable-loop-block.ll
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/workitem-intrinsics.ll
    M llvm/test/Analysis/DivergenceAnalysis/NVPTX/daorder.ll
    M llvm/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll
    M llvm/test/Analysis/DivergenceAnalysis/NVPTX/hidden_diverge.ll
    M llvm/test/Analysis/DivergenceAnalysis/NVPTX/irreducible.ll

  Log Message:
  -----------
  RFC: Uniformity Analysis for Irreducible Control Flow

Uniformity analysis is a generalization of divergence analysis to
include irreducible control flow:

  1. The proposed spec presents a notion of "maximal convergence" that
     captures the existing convention of converging threads at the
     headers of natual loops.

  2. Maximal convergence is then extended to irreducible cycles. The
     identity of irreducible cycles is determined by the choices made
     in a depth-first traversal of the control flow graph. Uniformity
     analysis uses criteria that depend only on closed paths and not
     cycles, to determine maximal convergence. This makes it a
     conservative analysis that is independent of the effect of DFS on
     CycleInfo.

  3. The analysis is implemented as a template that can be
     instantiated for both LLVM IR and Machine IR.

Validation:
  - passes existing tests for divergence analysis
  - passes new tests with irreducible control flow
  - passes equivalent tests in MIR and GMIR

Based on concepts originally outlined by
Nicolai Haehnle <nicolai.haehnle at amd.com>

With contributions from Ruiling Song <ruiling.song at amd.com> and
Jay Foad <jay.foad at amd.com>.

Support for GMIR and lit tests for GMIR/MIR added by
Yashwant Singh <yashwant.singh at amd.com>.

Differential Revision: https://reviews.llvm.org/D130746