[all-commits] [llvm/llvm-project] f1dcb9: [SDAG] neg x with only low bit demanded is x

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1dcb9c36fe46c97a8f22c8b2544fb25d2e4cb61
      https://github.com/llvm/llvm-project/commit/f1dcb9c36fe46c97a8f22c8b2544fb25d2e4cb61
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll

  Log Message:
  -----------
  [SDAG] neg x with only low bit demanded is x

We have a version of this transform in InstCombine, but surprisingly not in SDAG.  Even more surprisingly, this benefits RISCV, but no other target. This was surprising enough I double checked my build configuration to make sure all targets were enabled; they appear to be.

Differential Revision: https://reviews.llvm.org/D140324