[all-commits] [llvm/llvm-project] 828b1c: [RISCV] Match neg (and x, 1) to two shifts to impr...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 828b1c55cb7f5b327ea7399bc6f6386ecad14972
      https://github.com/llvm/llvm-project/commit/828b1c55cb7f5b327ea7399bc6f6386ecad14972
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/pr58511.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/select.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
    M llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Match neg (and x, 1) to two shifts to improve codesize

The negate operation is never compressible (as the destination and rs1 register must differ). The two shift versions will be equal size if the input GPR is reused, or smaller if this is the only use of the input.

For clarity, the operation being performed is (select (low-bit-of x), -1, 0).

Differential Revision: https://reviews.llvm.org/D140319