[all-commits] [llvm/llvm-project] 9b92f7: Revert "Reland "[TargetLowering] Teach DemandedBit...

[Saleem Abdulrasool via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9b92f70d4758f75903ce93feaba5098130820d40
      https://github.com/llvm/llvm-project/commit/9b92f70d4758f75903ce93feaba5098130820d40
  Author: Saleem Abdulrasool <compnerd at compnerd.org>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

  Log Message:
  -----------
  Revert "Reland "[TargetLowering] Teach DemandedBits about VSCALE""

This reverts commit 3010f60381bcd828d1b409cfaa576328bcd05bbc.

This change introduced undefined behaviour (reported at
https://reviews.llvm.org/D138508#inline-1352840).  Additionally, it
appears to be responsible for a mis-compilation on RISCV64 with the
vector extension (https://github.com/llvm/llvm-project/issues/59594).
The commit message indicates that this is meant to be ARM64 specific
though is a generic selection change.