[all-commits] [llvm/llvm-project] 6a907a: [RISCV] Add codegen support for RISCV XVentanaCond...

[Kautuk Consul via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a907a41f46ed03b1327eea0177a1bdb01d9a5c2
      https://github.com/llvm/llvm-project/commit/6a907a41f46ed03b1327eea0177a1bdb01d9a5c2
  Author: Kautuk Consul <kconsul at ventanamicro.com>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
    M llvm/test/CodeGen/RISCV/select.ll
    A llvm/test/CodeGen/RISCV/xventanacondops.ll

  Log Message:
  -----------
  [RISCV] Add codegen support for RISCV XVentanaCondOps Extension

This patch adds codegen support for part of XVentanaCondOps extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondOps specification.

The specification for XVentanaCondOps extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Co-authored-by: Mikhail Gudim <mgudim at ventanamicro.com>

Differential Revision: https://reviews.llvm.org/D139394