[all-commits] [llvm/llvm-project] 0d6d05: [AArch64] Add alias predicate-as-counter register ...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0
      https://github.com/llvm/llvm-project/commit/0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0
  Author: Caroline.Concatto at arm.com <carcon01 at ip-10-252-16-47.eu-west-1.compute.internal>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
    M llvm/test/MC/AArch64/SVE/pfalse.s

  Log Message:
  -----------
  [AArch64] Add alias predicate-as-counter register for PFALSE

According to:
https://developer.arm.com/documentation/ddi0602/2022-09/
PFALSE should:
"...an assembler must also accept predicate-as-counter register
name for the destination predicate register."

Differential Revision: https://reviews.llvm.org/D140301