[all-commits] [llvm/llvm-project] 1456b6: [RISCV] Convert some tests to opaque pointers (NFC)

Nikita Popov via All-commits all-commits at lists.llvm.org
Mon Dec 19 04:01:45 PST 2022 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1456b68686808fa7c6ed7327aba65b639f81d5b8
      https://github.com/llvm/llvm-project/commit/1456b68686808fa7c6ed7327aba65b639f81d5b8
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2022-12-19 (Mon, 19 Dec 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/add-imm.ll
    M llvm/test/CodeGen/RISCV/addrspacecast.ll
    M llvm/test/CodeGen/RISCV/alloca.ll
    M llvm/test/CodeGen/RISCV/alu16.ll
    M llvm/test/CodeGen/RISCV/alu8.ll
    M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-load-store.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/blockaddress.ll
    M llvm/test/CodeGen/RISCV/branch.ll
    M llvm/test/CodeGen/RISCV/byval.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/calls.ll
    M llvm/test/CodeGen/RISCV/cmp-bool.ll
    M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
    M llvm/test/CodeGen/RISCV/compress-float.ll
    M llvm/test/CodeGen/RISCV/compress-inline-asm.ll
    M llvm/test/CodeGen/RISCV/compress.ll
    M llvm/test/CodeGen/RISCV/disjoint.ll
    M llvm/test/CodeGen/RISCV/double-convert-strict.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/dwarf-eh.ll
    M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
    M llvm/test/CodeGen/RISCV/elf-preemption.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/fixups-diff.ll
    M llvm/test/CodeGen/RISCV/fixups-relax-diff.ll
    M llvm/test/CodeGen/RISCV/float-convert-strict.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-mem.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/fp-imm.ll
    M llvm/test/CodeGen/RISCV/fp128.ll
    M llvm/test/CodeGen/RISCV/fp16-promote.ll
    M llvm/test/CodeGen/RISCV/frame-info.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
    M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
    M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
    M llvm/test/CodeGen/RISCV/imm-cse.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/indirectbr.ll
    M llvm/test/CodeGen/RISCV/init-array.ll
    M llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
    M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll
    M llvm/test/CodeGen/RISCV/isel-optnone.ll
    M llvm/test/CodeGen/RISCV/jumptable.ll
    M llvm/test/CodeGen/RISCV/large-stack.ll
    M llvm/test/CodeGen/RISCV/legalize-fneg.ll
    M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
    M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
    M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
    M llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
    M llvm/test/CodeGen/RISCV/machine-cse.ll
    M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
    M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
    M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll
    M llvm/test/CodeGen/RISCV/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/mir-target-flags.ll
    M llvm/test/CodeGen/RISCV/musttail-call.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/option-nopic.ll
    M llvm/test/CodeGen/RISCV/option-pic.ll
    M llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll
    M llvm/test/CodeGen/RISCV/pic-models.ll
    M llvm/test/CodeGen/RISCV/pr51206.ll
    M llvm/test/CodeGen/RISCV/pr58025.ll
    M llvm/test/CodeGen/RISCV/pr58286.ll
    M llvm/test/CodeGen/RISCV/prefetch.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/remat.ll
    M llvm/test/CodeGen/RISCV/reserved-regs.ll
    M llvm/test/CodeGen/RISCV/rv32zba.ll
    M llvm/test/CodeGen/RISCV/rv64-large-stack.ll
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
    M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
    M llvm/test/CodeGen/RISCV/rvv/pr52475.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
    M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
    M llvm/test/CodeGen/RISCV/saverestore.ll
    M llvm/test/CodeGen/RISCV/select-cc.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/shl-demanded.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap.ll
    M llvm/test/CodeGen/RISCV/sink-icmp.ll
    M llvm/test/CodeGen/RISCV/split-offsets.ll
    M llvm/test/CodeGen/RISCV/split-sp-adjust.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/stack-slot-size.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/RISCV/tagged-globals.ll
    M llvm/test/CodeGen/RISCV/tail-calls.ll
    M llvm/test/CodeGen/RISCV/thread-pointer.ll
    M llvm/test/CodeGen/RISCV/tls-models.ll
    M llvm/test/CodeGen/RISCV/trunc-free.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
    M llvm/test/CodeGen/RISCV/wide-mem.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
    M llvm/test/CodeGen/RISCV/zfh-imm.ll
    M llvm/test/CodeGen/RISCV/zfhmin-imm.ll

  Log Message:
  -----------
  [RISCV] Convert some tests to opaque pointers (NFC)

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