[all-commits] [llvm/llvm-project] da7415: [RISCV] Add support for predicating AND/OR/XOR/ADD...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: da7415acdafb280d052da084edc4ce8747d6574c
      https://github.com/llvm/llvm-project/commit/da7415acdafb280d052da084edc4ce8747d6574c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-16 (Fri, 16 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/select-binop-identity.ll
    M llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll

  Log Message:
  -----------
  [RISCV] Add support for predicating AND/OR/XOR/ADD/SUB with short-forward-branch-opt.

sifive-7-series can predicate ALU instructions in the shadow of a
branch not just move instructions.

This patch implements analyzeSelect/optimizeSelect to predicate
these operations. This is based on ARM's implementation which can
predicate using flags and condition codes.

I've restricted it to just the instructions we have test cases for,
but it can be extended in the future.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140053