[all-commits] [llvm/llvm-project] b5efec: [CodeGen] Additional Register argument to storeReg...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5efec4b27bf5451a4fae74973f7a7a28fbc6108
      https://github.com/llvm/llvm-project/commit/b5efec4b27bf5451a4fae74973f7a7a28fbc6108
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2022-12-17 (Sat, 17 Dec 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/CodeGen/RegAllocFast.cpp
    M llvm/lib/CodeGen/RegisterScavenging.cpp
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/ARC/ARCInstrInfo.cpp
    M llvm/lib/Target/ARC/ARCInstrInfo.h
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
    M llvm/lib/Target/ARM/Thumb1InstrInfo.h
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/lib/Target/ARM/Thumb2InstrInfo.h
    M llvm/lib/Target/AVR/AVRInstrInfo.cpp
    M llvm/lib/Target/AVR/AVRInstrInfo.h
    M llvm/lib/Target/BPF/BPFInstrInfo.cpp
    M llvm/lib/Target/BPF/BPFInstrInfo.h
    M llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
    M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
    M llvm/lib/Target/CSKY/CSKYInstrInfo.h
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
    M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
    M llvm/lib/Target/Lanai/LanaiInstrInfo.h
    M llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
    M llvm/lib/Target/M68k/M68kFrameLowering.h
    M llvm/lib/Target/M68k/M68kInstrInfo.cpp
    M llvm/lib/Target/M68k/M68kInstrInfo.h
    M llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
    M llvm/lib/Target/MSP430/MSP430InstrInfo.h
    M llvm/lib/Target/Mips/MipsInstrInfo.h
    M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
    M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
    M llvm/lib/Target/Sparc/SparcInstrInfo.h
    M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
    M llvm/lib/Target/VE/VEInstrInfo.cpp
    M llvm/lib/Target/VE/VEInstrInfo.h
    M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.h
    M llvm/lib/Target/XCore/XCoreFrameLowering.cpp
    M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
    M llvm/lib/Target/XCore/XCoreInstrInfo.h

  Log Message:
  -----------
  [CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot

With D134950, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful with the delegate callback. AMDGPU propagates
the virtual register flags maintained in the target file itself. They are useful
to identify a certain type of machine operands while inserting spill stores and
reloads. Since RegAllocFast spills the physical register itself, there is no way
its virtual register can be mapped back to retrieve the flags. It can be solved
by passing the virtual register as an additional argument. This argument has no
use when the spill interfaces are called during the greedy allocator or even the
PrologEpilogInserter and can pass a null register in such cases.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D138656