[all-commits] [llvm/llvm-project] 5692a7: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5692a7e84e1273921099f9fbbaf353cd000df9bb
      https://github.com/llvm/llvm-project/commit/5692a7e84e1273921099f9fbbaf353cd000df9bb
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2022-12-17 (Sat, 17 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/frame-index.mir
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    A llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

  Log Message:
  -----------
  [AMDGPU] Callee must always spill writelane VGPRs

Since the writelane instruction used for SGPR spills can
modify inactive lanes, the callee must preserve the VGPR
this instruction modifies even if it was marked Caller-saved.

Reviewed By: arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D124192