[all-commits] [llvm/llvm-project] cfd594: [SROA] `isVectorPromotionViable()`: memory intrins...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cfd594f8bb5e779c81171e7c1e61ae8436efabd3
      https://github.com/llvm/llvm-project/commit/cfd594f8bb5e779c81171e7c1e61ae8436efabd3
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-16 (Fri, 16 Dec 2022)

  Changed paths:
    M clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
    M llvm/lib/Transforms/Scalar/SROA.cpp
    M llvm/test/CodeGen/AMDGPU/v1024.ll
    M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
    M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-from-same-alloca.ll
    M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
    M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-memcpy.ll
    M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
    M llvm/test/DebugInfo/X86/sroasplit-1.ll
    M llvm/test/DebugInfo/X86/sroasplit-4.ll
    M llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
    M llvm/test/Transforms/SROA/address-spaces.ll
    M llvm/test/Transforms/SROA/alignment.ll
    M llvm/test/Transforms/SROA/alloca-address-space.ll
    M llvm/test/Transforms/SROA/basictest.ll
    M llvm/test/Transforms/SROA/pointer-offset-size.ll
    M llvm/test/Transforms/SROA/scalable-vectors.ll
    M llvm/test/Transforms/SROA/slice-width.ll
    M llvm/test/Transforms/SROA/tbaa-struct.ll
    M llvm/test/Transforms/SROA/tbaa-struct2.ll
    M llvm/test/Transforms/SROA/vector-promotion.ll

  Log Message:
  -----------
  [SROA] `isVectorPromotionViable()`: memory intrinsics operate on vectors of bytes (take 3)

* This is a recommit of 3c4d2a03968ccf5889bacffe02d6fa2443b0260f,
* which was reverted in 25f01d593ce296078f57e872778b77d074ae5888,
  because it exposed a miscompile in PPC backend,  which was resolved
  in https://reviews.llvm.org/D140089 / cb3f415cd2019df7d14683842198bc4b7a492bc5.
* which was a recommit of cf624b23bc5d5a6161706d1663def49380ff816a,
* which was reverted in 5cfc22cafe3f2465e0bb324f8daba82ffcabd0df,
  because the cut-off on the number of vector elements was not low enough,
  and it triggered both SDAG SDNode operand number assertions,
  5and caused compile time explosions in some cases.

Let's try with something really *REALLY* conservative first,
just to get somewhere, and try to bump it later.

FIXME: should this respect TTI reg width * num vec regs?

Original commit message:

Now, there's a big caveat here - these bytes
are abstract bytes, not the i8 we have in LLVM,
so strictly speaking this is not exactly legal,
see e.g. https://github.com/AliveToolkit/alive2/issues/860
^ the "bytes" "could" have been a pointer,
and loading it as an integer inserts an implicit ptrtoint.

But at the same time,
InstCombine's `InstCombinerImpl::SimplifyAnyMemTransfer()`
would expand a memtransfer of 1/2/4/8 bytes
into integer-typed load+store,
so this isn't exactly a new problem.

Note that in memory, poison is byte-wise,
so we really can't widen elements,
but SROA seems to be inconsistent here.

Fixes #59116.