[all-commits] [llvm/llvm-project] ffedf4: [SelectionDAG] Do not second-guess alignment for a...

[Andrew Savonichev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ffedf47d8b793e07317f82f9c2a5f5425ebb71ad
      https://github.com/llvm/llvm-project/commit/ffedf47d8b793e07317f82f9c2a5f5425ebb71ad
  Author: Andrew Savonichev <andrew.savonichev at gmail.com>
  Date:   2022-12-15 (Thu, 15 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    M llvm/test/CodeGen/AArch64/preferred-alignment.ll
    M llvm/test/CodeGen/AArch64/seh-finally.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/ARM/ssp-data-layout.ll
    M llvm/test/CodeGen/BPF/pr57872.ll
    M llvm/test/CodeGen/BPF/undef.ll
    M llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
    M llvm/test/CodeGen/Mips/atomic64.ll
    M llvm/test/CodeGen/Mips/cconv/byval.ll
    M llvm/test/CodeGen/Mips/cconv/return-struct.ll
    M llvm/test/CodeGen/Mips/largeimmprinting.ll
    M llvm/test/CodeGen/Mips/o32_cc_byval.ll
    M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
    M llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
    M llvm/test/CodeGen/PowerPC/aix-sret-param.ll
    M llvm/test/CodeGen/PowerPC/byval.ll
    M llvm/test/CodeGen/PowerPC/structsinregs.ll
    M llvm/test/CodeGen/PowerPC/varargs-struct-float.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/mem64.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/Thumb2/mve-stack.ll
    M llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
    M llvm/test/CodeGen/VE/Scalar/atomic_load.ll
    M llvm/test/CodeGen/VE/Scalar/atomic_swap.ll
    M llvm/test/CodeGen/WebAssembly/PR40172.ll
    M llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
    M llvm/test/CodeGen/X86/fast-isel-call.ll
    M llvm/test/CodeGen/X86/load-local-v3i129.ll
    M llvm/test/CodeGen/X86/pr44140.ll
    M llvm/test/CodeGen/X86/ssp-data-layout.ll
    M llvm/test/CodeGen/X86/win-cleanuppad.ll
    M llvm/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll
    M llvm/test/DebugInfo/AArch64/frameindices.ll
    M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
    M llvm/test/DebugInfo/X86/dbg-addr.ll
    M llvm/test/DebugInfo/X86/dbg-declare-alloca.ll
    M llvm/test/DebugInfo/X86/sret.ll
    M llvm/test/DebugInfo/assignment-tracking/X86/nested-loop-frags.ll

  Log Message:
  -----------
  [SelectionDAG] Do not second-guess alignment for alloca

Alignment of an alloca in IR can be lower than the preferred alignment
on purpose, but this override essentially treats the preferred
alignment as the minimum alignment.

The patch changes this behavior to always use the specified
alignment. If alignment is not set explicitly in LLVM IR, it is set to
DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign.

Tests are changed as well: explicit alignment is increased to match
the preferred alignment if it changes output, or omitted when it is
hard to determine the right value (e.g. for pointers, some structs, or
weird types).

Differential Revision: https://reviews.llvm.org/D135462