[all-commits] [llvm/llvm-project] 3010f6: Reland "[TargetLowering] Teach DemandedBits about ...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3010f60381bcd828d1b409cfaa576328bcd05bbc
      https://github.com/llvm/llvm-project/commit/3010f60381bcd828d1b409cfaa576328bcd05bbc
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2022-12-15 (Thu, 15 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

  Log Message:
  -----------
  Reland "[TargetLowering] Teach DemandedBits about VSCALE"

Reland with a fixup to avoid converting APInts to int64_t which allowed for
overflows (UB) with sufficiently high/low multiplier values.

This allows DemandedBits to see the result of VSCALE will be at most
VScaleMax * some compile-time constant. This relies on the vscale_range()
attribute being present on the function, with a max set. (This is done by
default when clang is targeting AArch64+SVE).

Using this various redundant operations (zexts, sexts, ands, ors, etc)
can be eliminated.

Differential Revision: https://reviews.llvm.org/D138508