[all-commits] [llvm/llvm-project] 827fb6: [RISCV] Add IsSignExtendingOpW to the Zknh SHA256 ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 827fb6c38ca59236e634f69a497a71fe94e3e99b
      https://github.com/llvm/llvm-project/commit/827fb6c38ca59236e634f69a497a71fe94e3e99b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-14 (Wed, 14 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
    M llvm/test/CodeGen/RISCV/sextw-removal.ll

  Log Message:
  -----------
  [RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.

On RV64 these instructions produce a 32-bit value and sign extend
to 64-bits.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140036