[all-commits] [llvm/llvm-project] 3e7dad: [RISCV] Add a bit to TSFlags to mark SignExtending...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e7dad22f111b9256e79dcb9cdb1c21ff0fd73dc
      https://github.com/llvm/llvm-project/commit/3e7dad22f111b9256e79dcb9cdb1c21ff0fd73dc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-14 (Wed, 14 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

  Log Message:
  -----------
  [RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.

Instead of switching on the opcode in SExtWRemoval, we can use a
bit in TSFlags. This reduces the amount of code that needs to be
generated to implement the switch. The opcodes are scattered throughout
the opcode enum, so the switch isn't very densely packed.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D139965