[all-commits] [llvm/llvm-project] c86a87: [RISCV] Add Syntacore SCR1 CPU model
dnpetrov-sc via All-commits
all-commits at lists.llvm.org
Wed Dec 14 00:50:02 PST 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: c86a878e8995d54a5b950098e81f0d3bf153aded
https://github.com/llvm/llvm-project/commit/c86a878e8995d54a5b950098e81f0d3bf153aded
Author: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Date: 2022-12-14 (Wed, 14 Dec 2022)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note.c
M llvm/include/llvm/Support/RISCVTargetParser.def
M llvm/lib/Target/RISCV/RISCV.td
A llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
Log Message:
-----------
[RISCV] Add Syntacore SCR1 CPU model
SCR1 is available at https://github.com/syntacore/scr1
'syntacore-scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'syntacore-scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.
SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D139302
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