[all-commits] [llvm/llvm-project] 14d4cd: [X86] Don't zero out %eax if both %al and %ah are ...

[Bill Wendling via All-commits]

  Branch: refs/heads/arcpatch-D139679
  Home:   https://github.com/llvm/llvm-project
  Commit: 14d4cddc5506fb0fd3c4ac556b4edd970aa151eb
      https://github.com/llvm/llvm-project/commit/14d4cddc5506fb0fd3c4ac556b4edd970aa151eb
  Author: Bill Wendling <morbo at google.com>
  Date:   2022-12-13 (Tue, 13 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    A llvm/test/CodeGen/X86/zero-call-used-regs-i386.ll

  Log Message:
  -----------
  [X86] Don't zero out %eax if both %al and %ah are used

The iterator over super and sub registers doesn't include both 8-bit
registers in its list. So if both registers are used and only one of
them is live on return, then we need to make sure that the other 8-bit
register is also marked as live and not zeroed out.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D139679