[all-commits] [llvm/llvm-project] 899226: [LoongArch] Add custom parser for atomic instructi...

[wanglei via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 899226adac2cd07938b318e100fdca1eb9c4b1e1
      https://github.com/llvm/llvm-project/commit/899226adac2cd07938b318e100fdca1eb9c4b1e1
  Author: wanglei <wanglei at loongson.cn>
  Date:   2022-12-13 (Tue, 13 Dec 2022)

  Changed paths:
    M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
    M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp
    M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h
    M llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
    M llvm/test/MC/LoongArch/Basic/Integer/atomic.s
    M llvm/test/MC/LoongArch/Basic/Integer/invalid64.s

  Log Message:
  -----------
  [LoongArch] Add custom parser for atomic instructions' memory operand

In order to be compatible with the form of the atomic instruction in
GAS that accepts the fourth operand as 0 (i.e. `am* $rd, $rk, $rj, 0`),
we need to treat `$rj, 0` as one operand, but only print `$rj`.

For this, the number of result operands of inline assembly memory
operand `ZB` constraint is modified to 2 (reg + 0).

Restrictions on register usage in `am*` instructions have also been
adjusted. When `$rd` is equal to `$r0`, the instruction must be
considered legal, because of some special usage like `PseudoUNIMP`.

Reviewed By: SixWeining, xen0n

Differential Revision: https://reviews.llvm.org/D139303