[all-commits] [llvm/llvm-project] f7cdcc: [NFC][Codegen][X86] Revisit interleaved load codeg...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7cdcc288454edd1c778c26499a646d20767119c
      https://github.com/llvm/llvm-project/commit/f7cdcc288454edd1c778c26499a646d20767119c
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-13 (Tue, 13 Dec 2022)

  Changed paths:
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    A llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll

  Log Message:
  -----------
  [NFC][Codegen][X86] Revisit interleaved load codegen tests

This matches the coverage with the Costmodel tests,
adds stride 5/7/8, and improves AVX512 checks.

I *think* i've compressed check prefixes
as much as possible, but it's a bit hard to tell.
But hey, at one no longer has to fight against FileCheck+UTC :).