[all-commits] [llvm/llvm-project] dfc8ab: Revert "Revert "[AArch64] Select SMULL for zero ex...

[Zain Jaffal via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dfc8ab2e25dac2baddb36023991e6f88e12eb4bb
      https://github.com/llvm/llvm-project/commit/dfc8ab2e25dac2baddb36023991e6f88e12eb4bb
  Author: Zain Jaffal <z_jaffal at apple.com>
  Date:   2022-12-12 (Mon, 12 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll

  Log Message:
  -----------
  Revert "Revert "[AArch64] Select SMULL for zero extended vectors when top bit is zero""

This reverts commit c07a01c2bb0d1f95689f809fd5be23829e364393.


  Commit: ebae917294e680132fe1a3bc586a332dd47de8d0
      https://github.com/llvm/llvm-project/commit/ebae917294e680132fe1a3bc586a332dd47de8d0
  Author: Zain Jaffal <z_jaffal at apple.com>
  Date:   2022-12-12 (Mon, 12 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll

  Log Message:
  -----------
  Recommit "[AArch64] Select SMULL for zero extended vectors when top bit is zero"

This is a recommit of f9e0390751cb5eefbbbc191f851c52422acacab1
The previous commit failed to handle cases where the zero extended operand is an extended `BUILD_VECTOR`.
We don't replace zext with a sext operand to select smull if any operand is `BUILD_VECTOR`

Original commit message:

we can safely replace a `zext` instruction with `sext` if the top bit is zero. This is useful because we can select `smull` when both operands are sign extended.

Reviewed By: fhahn, dmgreen

Differential Revision: https://reviews.llvm.org/D134711


Compare: https://github.com/llvm/llvm-project/compare/6de861125aee...ebae917294e6