[all-commits] [llvm/llvm-project] 8812b6: [AArch64][SVE][Fixed length] Fix div miscompile

[Peter Waller via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8812b6eed7b2328d6e2739071f6460bfd47ac8e2
      https://github.com/llvm/llvm-project/commit/8812b6eed7b2328d6e2739071f6460bfd47ac8e2
  Author: Peter Waller <peter.waller at arm.com>
  Date:   2022-12-12 (Mon, 12 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll

  Log Message:
  -----------
  [AArch64][SVE][Fixed length] Fix div miscompile

The prior code worked before SVE DIV was enabled 128 bit vectors.
With 128 bit vectors, when run on a 256 bit machine, it would split and
do a signed unpack, but this resulted in one full vector and one empty
vector with a half-sized predicate. The effect was that only half the
elements were treated correctly.

The fix is to bisect the vector, sign extend, do the division, truncate
and then concat.

Fixes #59357.

Differential Revision: https://reviews.llvm.org/D139618