[all-commits] [llvm/llvm-project] 7b3650: [RISCV][CodeGen] Account for LMUL for Vector Integ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b3650285442f0c1cf7f7417706c0c66f9b5262c
      https://github.com/llvm/llvm-project/commit/7b3650285442f0c1cf7f7417706c0c66f9b5262c
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2022-12-06 (Tue, 06 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions

It is likley that subtargets act differently for a vector load store instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.

Differential Revision: https://reviews.llvm.org/D137429