[all-commits] [llvm/llvm-project] ac1ec9: [RISCV] Share code for fixed offsets adjustRegs (t...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac1ec9e2904a696e360b40572c3b3c29d67981ef
      https://github.com/llvm/llvm-project/commit/ac1ec9e2904a696e360b40572c3b3c29d67981ef
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-11-30 (Wed, 30 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/large-stack.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)

This reuses the existing optimized implementation of adjustReg, and commons up code. This has the effect of enabling two code changes for the new caller. First, we enable the "split andi" lowering (with no alignment requirement), and second we use a sub with smaller constant in register instead of a add with negative constant in register.

Differential Revision: https://reviews.llvm.org/D132839