[all-commits] [llvm/llvm-project] b883e9: [X86] Add test case for (any_extend (bitcast (conc...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b883e9f3929c44dd7cdf5d94df3973fbf9f879f2
      https://github.com/llvm/llvm-project/commit/b883e9f3929c44dd7cdf5d94df3973fbf9f879f2
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-11-25 (Fri, 25 Nov 2022)

  Changed paths:
    M llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

  Log Message:
  -----------
  [X86] Add test case for (any_extend (bitcast (concat_vectors (and (vYi1 setcc, vYi1 x), undef)))) pattern

Similar pattern to a regression identified in D127115


  Commit: 6fd0ae39be79bdb686e4cc966e4cdee9950e2645
      https://github.com/llvm/llvm-project/commit/6fd0ae39be79bdb686e4cc966e4cdee9950e2645
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-11-25 (Fri, 25 Nov 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

  Log Message:
  -----------
  [X86] combineScalarAndWithMaskSetcc - handle (concat_vectors (and (vYi1 setcc, vYi1 x), undef)) patterns

If one of the AND operands is a setcc then we're implicitly zeroing the upper mask bits

Similar pattern to regressions identified in D127115 (masked comparisons)


Compare: https://github.com/llvm/llvm-project/compare/6a95e67323dd...6fd0ae39be79