[all-commits] [llvm/llvm-project] 4e56aa: [X86] Schedule scalar movsx/movzx load+extend ops ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e56aa252fc983574e32a0cb8b73333831f66700
      https://github.com/llvm/llvm-project/commit/4e56aa252fc983574e32a0cb8b73333831f66700
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-11-06 (Sun, 06 Nov 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrExtension.td
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td
    M llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/SLM/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s

  Log Message:
  -----------
  [X86] Schedule scalar movsx/movzx load+extend ops as WriteLoad instead of WriteALULd

Although some very old x86 hardware would perform the extension as a later stage, every target we have a scheduler for always performs this as part of the load-op (avoid ALU pipes etc.). If anyone wants to model very old hardware they can always override this.

This patch just tags these as WriteLoad directly and removes unnecessary overrides - this cleans up some latency/throughput tests as they aren't being badly modelled as folded ALU ops