[all-commits] [llvm/llvm-project] 4a6ef0: [RISCV] Change SEXT_B/SEXT_H/ZEXT_H_RV64 handling ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4a6ef0078cd0ce5c6622cb141bca5cfb9bee5f22
      https://github.com/llvm/llvm-project/commit/4a6ef0078cd0ce5c6622cb141bca5cfb9bee5f22
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-03 (Thu, 03 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

  Log Message:
  -----------
  [RISCV] Change SEXT_B/SEXT_H/ZEXT_H_RV64 handling in isAllUsesReadW in SExtWRemoval.

These instrucitons only use the lower 8 or 16 bits. We don't need
to look across them.


  Commit: 2fb1324736f69391636297f973e697c41e2d7a61
      https://github.com/llvm/llvm-project/commit/2fb1324736f69391636297f973e697c41e2d7a61
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-03 (Thu, 03 Nov 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

  Log Message:
  -----------
  [RISCV] Add FMV_H_X/FMV_W_X/FCVT_H_W/FCVT_H_WU to isAllUsesReadW in SExtWRemoval.

The instructions only read the lower 16 or 32 bits of a GPR.


Compare: https://github.com/llvm/llvm-project/compare/bf1e235695a7...2fb1324736f6