[all-commits] [llvm/llvm-project] f62d8a: [AArch64] Compare BFI and ORR with left-shifted op...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f62d8a1a5044df7b8d72033d056375b4ab256012
      https://github.com/llvm/llvm-project/commit/f62d8a1a5044df7b8d72033d056375b4ab256012
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-11-03 (Thu, 03 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
    M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
    M llvm/test/CodeGen/AArch64/arm64-strict-align.ll
    M llvm/test/CodeGen/AArch64/arm64_32.ll
    M llvm/test/CodeGen/AArch64/bfis-in-loop.ll
    M llvm/test/CodeGen/AArch64/bitfield-insert.ll
    M llvm/test/CodeGen/AArch64/build-pair-isel.ll
    M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
    M llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
    M llvm/test/CodeGen/AArch64/load-combine.ll
    M llvm/test/CodeGen/AArch64/logic-shift.ll
    M llvm/test/CodeGen/AArch64/nontemporal-load.ll
    M llvm/test/CodeGen/AArch64/rotate-extract.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
    M llvm/test/CodeGen/AArch64/urem-seteq.ll
    M llvm/test/CodeGen/AArch64/vec_uaddo.ll
    M llvm/test/CodeGen/AArch64/vec_umulo.ll

  Log Message:
  -----------
  [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection.

Before this patch:
- For `r = or op0, op1`, `tryBitfieldInsertOpFromOr` combines it to BFI when
  1) one of the two operands is bit-field-positioning or bit-field-extraction op; and
  2) bits from the two operands don't overlap

After this patch:
- Right before OR is combined to BFI, evaluates if ORR with left-shifted operand is better.

A motivating example (https://godbolt.org/z/rnMrzs5vn, which is added as a test case in `test_orr_not_bfi` in `CodeGen/AArch64/bitfield-insert.ll`)

For IR:
```
define i64 @test_orr_not_bfxil(i64 %0) {
  %2 = and i64 %0, 127
  %3 = lshr i64 %0, 1
  %4 = and i64 %3, 16256
  %5 = or i64 %4, %2
  ret i64 %5
}
```

Before:
```
   lsr     x8, x0, #1
   and     x8, x8, #0x3f80
   bfxil   x8, x0, #0, #7
```

After:
```
   ubfx x8, x0, #8, #7
   and x9, x0, #0x7f
   orr x0, x9, x8, lsl #7
```

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D135102