[all-commits] [llvm/llvm-project] 150fc7: [AggressiveInstCombine] Avoid load merge/widen if ...

[bipmis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 150fc73ddab65901e2f89c70af436706b859eef8
      https://github.com/llvm/llvm-project/commit/150fc73ddab65901e2f89c70af436706b859eef8
  Author: bipmis <biplob.mishra at arm.com>
  Date:   2022-11-03 (Thu, 03 Nov 2022)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
    M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads

This patch is to address the test cases in which the load has to be inserted at a right point. This happens when there is a store b/w the loads.

This patch reverts the loads merge in all cases when stores are present b/w loads and will eventually be replaced with proper fix and test cases.

Differential Revision: https://reviews.llvm.org/D137333