[all-commits] [llvm/llvm-project] 9df924: [PowerPC] Add new DMR register classes to Future CPU.

[stefanp-ibm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9df924a634ac5ea702b0d8d0d8b737c819a98095
      https://github.com/llvm/llvm-project/commit/9df924a634ac5ea702b0d8d0d8b737c819a98095
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2022-11-03 (Thu, 03 Nov 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
    A llvm/lib/Target/PowerPC/PPCInstrFuture.td
    A llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    A llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td
    M llvm/lib/Target/PowerPC/PPCScheduleP9.td
    M llvm/test/CodeGen/PowerPC/future-check-features.ll
    A llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
    A llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
    A llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  [PowerPC] Add new DMR register classes to Future CPU.

A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.

This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.

Reviewed By: amyk, saghir

Differential Revision: https://reviews.llvm.org/D136366