[all-commits] [llvm/llvm-project] a20112: [AArch64]SME2 instructions that use ZTO operand

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a20112a74cb34fa967d10e07185167cbc2906c0d
      https://github.com/llvm/llvm-project/commit/a20112a74cb34fa967d10e07185167cbc2906c0d
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2022-11-03 (Thu, 03 Nov 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    A llvm/test/MC/AArch64/SME2/ldr-diagnostics.s
    A llvm/test/MC/AArch64/SME2/ldr.s
    A llvm/test/MC/AArch64/SME2/luti2-diagnostics.s
    A llvm/test/MC/AArch64/SME2/luti2.s
    A llvm/test/MC/AArch64/SME2/luti4-diagnostics.s
    A llvm/test/MC/AArch64/SME2/luti4.s
    A llvm/test/MC/AArch64/SME2/movt-diagnostics.s
    A llvm/test/MC/AArch64/SME2/movt.s
    A llvm/test/MC/AArch64/SME2/str-diagnostics.s
    A llvm/test/MC/AArch64/SME2/str.s
    A llvm/test/MC/AArch64/SME2/zero.s

  Log Message:
  -----------
  [AArch64]SME2 instructions that use ZTO operand

This patch adds the assembly/disassembly for the following instructions:
  ZERO (ZT0): Zero ZT0.
  LDR (ZT0): Load ZT0 register.
  STR (ZT0): Store ZT0 register.
  MOVT (scalar to ZT0): Move 8 bytes from general-purpose register to ZT0.
       (ZT0 to scalar): Move 8 bytes from ZT0 to general-purpose register.
 Consecutive:
   LUTI2 (single): Lookup table read with 2-bit indexes.
         (two registers): Lookup table read with 2-bit indexes.
         (four registers): Lookup table read with 2-bit indexes.
   LUTI4 (single): Lookup table read with 4-bit indexes.
         (two registers): Lookup table read with 4-bit indexes.
         (four registers): Lookup table read with 4-bit indexes.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

This patch also adds a new register class and operand for zt0
and a another index operand uimm3s8

Differential Revision: https://reviews.llvm.org/D136088