[all-commits] [llvm/llvm-project] b6ad7a: [RISCV] Prevent autovectorization using vscale wit...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b6ad7ab89ef5e1772e90248ee728fd955089c949
      https://github.com/llvm/llvm-project/commit/b6ad7ab89ef5e1772e90248ee728fd955089c949
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-11-02 (Wed, 02 Nov 2022)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/test/CodeGen/riscv-vector-bits-vscale-range.c
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    A llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll

  Log Message:
  -----------
  [RISCV] Prevent autovectorization using vscale with Zvl32b.

RVVBitsPerBlock is 64. If VLen==32, VLen/RVVBitsPerBlock is 0.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137280