[all-commits] [llvm/llvm-project] 88ac25: [MachineCSE] Allow PRE of instructions that read p...

[john-brawn-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88ac25b357aa2ac96fd1e44cd9fd12d2f1dd189a
      https://github.com/llvm/llvm-project/commit/88ac25b357aa2ac96fd1e44cd9fd12d2f1dd189a
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-11-02 (Wed, 02 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/MachineCSE.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
    M llvm/test/CodeGen/ARM/machine-cse-cmp.ll
    A llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll

  Log Message:
  -----------
  [MachineCSE] Allow PRE of instructions that read physical registers

Currently MachineCSE forbids PRE when the instruction reads a physical
register. Relax this so that it's allowed when the value being read is
the same as what would be read in the place the instruction would be
hoisted to.

This is being done in preparation for adding FPCR handling to the
AArch64 backend, in order to prevent it to from worsening the
generated code, but for targets that already have a similar register
it should improve things.

This patch affects code generation in several tests. The new code
looks better except for in Thumb2/LowOverheadLoops/memcall.ll where
we perform PRE but the LowOverheadLoops transformation then undoes
it. Also in AMDGPU/selectcc-opt.ll the CHECK makes things look worse,
but actually the function as a whole is better (as a MOV is PRE'd).

Differential Revision: https://reviews.llvm.org/D136675


  Commit: 2d8c1597e51c39d8db1c9428d65e6ef6d6a1d5c1
      https://github.com/llvm/llvm-project/commit/2d8c1597e51c39d8db1c9428d65e6ef6d6a1d5c1
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-11-02 (Wed, 02 Nov 2022)

  Changed paths:
    M llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
    M llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir
    M llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir
    M llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
    M llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
    M llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
    M llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir
    M llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

  Log Message:
  -----------
  [MIRVRegNamer] Avoid opcode hash collision

D121929 happens to cause CodeGen/MIR/AArch64/mirnamer.mir to fail due
to a hash collision caused by adding two extra opcodes. The collision
is only in the top 19 bits of the hashed opcode so fix this by just
using the whole hash (in fixed width hex for consistency) instead of
the top 5 decimal digits.

Differential Revision: https://reviews.llvm.org/D137155


Compare: https://github.com/llvm/llvm-project/compare/8f6c478fbfdd...2d8c1597e51c