[all-commits] [llvm/llvm-project] 78739f: [DAG] Enable combineShiftOfShiftedLogic folds afte...
Simon Pilgrim via All-commits
all-commits at lists.llvm.org
Sat Oct 29 04:30:23 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 78739fdb4d846c068ddd935d4cbd0474ff5fc6a9
https://github.com/llvm/llvm-project/commit/78739fdb4d846c068ddd935d4cbd0474ff5fc6a9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2022-10-29 (Sat, 29 Oct 2022)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/BPF/pr57872.ll
M llvm/test/CodeGen/Mips/cconv/return-struct.ll
M llvm/test/CodeGen/Mips/cconv/vector.ll
M llvm/test/CodeGen/Mips/load-store-left-right.ll
M llvm/test/CodeGen/Mips/unalignedload.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
M llvm/test/CodeGen/Thumb/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/bool-vector.ll
M llvm/test/CodeGen/X86/combine-bitreverse.ll
M llvm/test/CodeGen/X86/is_fpclass.ll
M llvm/test/CodeGen/X86/vector-sext.ll
Log Message:
-----------
[DAG] Enable combineShiftOfShiftedLogic folds after type legalization
This was disabled to prevent regressions, which appear to be just occurring on AMDGPU (at least in our current lit tests), which I've addressed by adding AMDGPUTargetLowering::isDesirableToCommuteWithShift overrides.
Fixes #57872
Differential Revision: https://reviews.llvm.org/D136042
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