[all-commits] [llvm/llvm-project] 1d4a57: [RISCV] Merge WriteLDW and WriteLDWU schedule clas...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d4a57bd12783ff98faed630e800e2c3675dd4d6
      https://github.com/llvm/llvm-project/commit/1d4a57bd12783ff98faed630e800e2c3675dd4d6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-28 (Fri, 28 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Merge WriteLDW and WriteLDWU schedule classes.

We don't distinquish signed vs unsigned for B and H loads.

Maybe this split was because LDWU isn't in RV32I? I don't think
that distinction matters to the scheduler. If your processor
only supports RV32I then having LWU in the SchedClass doesn't matter.
If your target supports RV64I, then LW and LWU are likely the same.