[all-commits] [llvm/llvm-project] 6a7944: [RISCV] Optimize i64 insertelt on RV32.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a794419cddb5e77178f2b048b5220051be758f8
      https://github.com/llvm/llvm-project/commit/6a794419cddb5e77178f2b048b5220051be758f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-28 (Fri, 28 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

  Log Message:
  -----------
  [RISCV] Optimize i64 insertelt on RV32.

We can use tail undisturbed vslide1down to insert into the vector.

This should make D136640 unneeded.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136738