[all-commits] [llvm/llvm-project] 3ac174: [mlir][nvvm] Introduce performance tuning directives

[Guray Ozen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ac17449cf988bfcde804a4cc532420ed1657595
      https://github.com/llvm/llvm-project/commit/3ac17449cf988bfcde804a4cc532420ed1657595
  Author: Guray Ozen <guray.ozen at gmail.com>
  Date:   2022-10-28 (Fri, 28 Oct 2022)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
    M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
    M mlir/test/Target/LLVMIR/nvvmir.mlir

  Log Message:
  -----------
  [mlir][nvvm] Introduce performance tuning directives

PTX programming models provides some performance tuning directives; see https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#performance-tuning-directives

The downstream compiler namely `ptxas` leverages these information for better register allocation or to handle other resource management that improves the performance.

This revision introduce all the kernel based directives to MLIR's NVVM dialect. The list is below
```
maxnreg			-> 	max register per thread in CTA
maxntid			-> 	max threads per CTA
reqntid			-> 	exact number of threads per CTA
minnctapersm		-> 	min CTA per SM
```

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D136931