[all-commits] [llvm/llvm-project] 00d93d: [LegalizeVectorOps][X86][RISCV] Expand vector S/US...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 00d93def778afa7fd117e615e4f6fb7645e25f49
      https://github.com/llvm/llvm-project/commit/00d93def778afa7fd117e615e4f6fb7645e25f49
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-27 (Thu, 27 Oct 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/ushl_sat_vec.ll
    M llvm/test/CodeGen/X86/sshl_sat_vec.ll
    M llvm/test/CodeGen/X86/ushl_sat_vec.ll

  Log Message:
  -----------
  [LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D136478