[all-commits] [llvm/llvm-project] 628467: [MachineCSE] Allow PRE of instructions that read p...

[john-brawn-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 628467e53f4ceecd2b5f0797f07591c66d9d9d2a
      https://github.com/llvm/llvm-project/commit/628467e53f4ceecd2b5f0797f07591c66d9d9d2a
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-10-27 (Thu, 27 Oct 2022)

  Changed paths:
    M llvm/lib/CodeGen/MachineCSE.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
    A llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll

  Log Message:
  -----------
  [MachineCSE] Allow PRE of instructions that read physical registers

Currently MachineCSE forbids PRE when the instruction reads a physical
register. Relax this so that it's allowed when the value being read is
the same as what would be read in the place the instruction would be
hoisted to.

This is being done in preparation for adding FPCR handling to the
AArch64 backend, in order to prevent it to from worsening the
generated code, but for targets that already have a similar register
it should improve things.

This patch affects code generation in several tests. The new code
looks better except for in Thumb2/LowOverheadLoops/memcall.ll where
we perform PRE but the LowOverheadLoops transformation then undoes
it. Also in AMDGPU/selectcc-opt.ll the CHECK makes things look worse,
but actually the function as a whole is better (as a MOV is PRE'd).

Differential Revision: https://reviews.llvm.org/D136675