[all-commits] [llvm/llvm-project] 54eead: [SDAG] avoid vector extract/insert around binop

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 54eeadcf442df91aed0fb7244fe7885cdf1b1f3d
      https://github.com/llvm/llvm-project/commit/54eeadcf442df91aed0fb7244fe7885cdf1b1f3d
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-10-26 (Wed, 26 Oct 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/cvt16.ll
    M llvm/test/CodeGen/X86/half.ll
    M llvm/test/CodeGen/X86/urem-vector-lkk.ll
    M llvm/test/CodeGen/X86/vec_shift5.ll

  Log Message:
  -----------
  [SDAG] avoid vector extract/insert around binop

scalar-to-vector (scalar binop (extractelt V, Idx), C) --> shuffle (vector binop V, C'), {Idx, -1, -1...}

We generally try to avoid ad-hoc vectorization in SDAG,
but the motivating case from issue #39482 escapes our
normal vectorization folds in IR. It seems like it should
always be a win to transform this pattern in cases where
we have the same vector type for input and output and the
target supports the vector operation. That avoids
transfers from vector to scalar and back.

In the x86 shift examples, we create the scalar-to-vector
node during legalization. I'm not sure if there's a more
general way to create the pattern for testing. (If so, I
could add tests for other targets.)

Differential Revision: https://reviews.llvm.org/D136713


  Commit: 1bd856fbe5be82062e2efff34be65c00b05f7510
      https://github.com/llvm/llvm-project/commit/1bd856fbe5be82062e2efff34be65c00b05f7510
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-10-26 (Wed, 26 Oct 2022)

  Changed paths:
    M llvm/test/Transforms/InstCombine/sub.ll

  Log Message:
  -----------
  [InstCombine] add tests for demanded bits of sub; NFC


Compare: https://github.com/llvm/llvm-project/compare/f85ce1b236d5...1bd856fbe5be