[all-commits] [llvm/llvm-project] a61b74: [RISCV] Use vslide1down for i64 insertelt on RV32.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a61b74889f54925949e94e68fd7548a0aa3cf709
      https://github.com/llvm/llvm-project/commit/a61b74889f54925949e94e68fd7548a0aa3cf709
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-26 (Wed, 26 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

  Log Message:
  -----------
  [RISCV] Use vslide1down for i64 insertelt on RV32.

Instead of using vslide1up, use vslide1down and build the other
direction. This avoids the overlap constraint early clobber of
vslide1up.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136735