[all-commits] [llvm/llvm-project] 9403a8: [GlobalISel][AArch64] Fix miscompile caused by wro...

[chenglin.bi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9403a8bc37baf840c2d55be1fc09b9e8bf3b6a74
      https://github.com/llvm/llvm-project/commit/9403a8bc37baf840c2d55be1fc09b9e8bf3b6a74
  Author: chenglin.bi <chenglin.bi at linaro.org>
  Date:   2022-10-26 (Wed, 26 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
    A llvm/test/CodeGen/AArch64/pr58431.ll

  Log Message:
  -----------
  [GlobalISel][AArch64] Fix miscompile caused by wrong G_ZEXT selection in GISel

The miscompile case's G_ZEXT has a G_FREEZE source.  Similar to D127154, this patch removed isDef32, relying on the AArch64MIPeephole optimizer to remove redundant SUBREG_TO_REG nodes also in GISel.

Fix #58431

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D136433