[all-commits] [llvm/llvm-project] 223f46: [RISCV] Add ORI to hasAllNBitUsers.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 223f466f4f39f052196e2883222666e5f2b8a01e
      https://github.com/llvm/llvm-project/commit/223f466f4f39f052196e2883222666e5f2b8a01e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-24 (Mon, 24 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/mul.ll

  Log Message:
  -----------
  [RISCV] Add ORI to hasAllNBitUsers.

If the immediate is negative with sufficient leading ones, then
the upper bits of the other operand aren't demanded.