[all-commits] [llvm/llvm-project] 440005: [AArch64]]SME2 multi-vec to multi-vec FP/INT down ...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 440005b3c3531901563b0a16834e013ecb973f66
      https://github.com/llvm/llvm-project/commit/440005b3c3531901563b0a16834e013ecb973f66
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2022-10-24 (Mon, 24 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    A llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s
    A llvm/test/MC/AArch64/SME2/fcvtzs.s
    A llvm/test/MC/AArch64/SME2/fcvtzu-diagnostics.s
    A llvm/test/MC/AArch64/SME2/fcvtzu.s
    A llvm/test/MC/AArch64/SME2/scvtf-diagnostics.s
    A llvm/test/MC/AArch64/SME2/scvtf.s
    A llvm/test/MC/AArch64/SME2/ucvtf-diagnostics.s
    A llvm/test/MC/AArch64/SME2/ucvtf.s

  Log Message:
  -----------
  [AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers

This patch implements:
 FCVTZS: Multi-vector floating-point convert to signed integer, rounding
         toward zero.
 FCVTZU: Multi-vector floating-point convert to unsigned integer,
        rounding toward zero.
 SCVTF: Multi-vector signed integer convert to floating-point.
 UCVTF: Multi-vector unsigned integer convert to floating-point.
for 2 and 4 registers

The reference can be found here:
    https://developer.arm.com/documentation/ddi0602/2022-09

    Depends on: D135563

Differential Revision: https://reviews.llvm.org/D135593