[all-commits] [llvm/llvm-project] 51b98d: GlobalISel: Precommit for artifact combine patches

petar-avramovic via All-commits all-commits at lists.llvm.org
Mon Oct 24 04:33:50 PDT 2022 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51b98db48771d46d9041fd145ea35234f7b723ac
      https://github.com/llvm/llvm-project/commit/51b98db48771d46d9041fd145ea35234f7b723ac
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2022-10-24 (Mon, 24 Oct 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

  Log Message:
  -----------
  GlobalISel: Precommit for artifact combine patches

Differential Revision: https://reviews.llvm.org/D117655


  Commit: f1aa5980466507407377e83162e86d17f1fa2543
      https://github.com/llvm/llvm-project/commit/f1aa5980466507407377e83162e86d17f1fa2543
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2022-10-24 (Mon, 24 Oct 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

  Log Message:
  -----------
  GlobalISel: Artifact combine merge-like and unmerge into copy

Recognize copy that is represented as split of a source register to
elements that were reassembled to another register with the same type.

Differential Revision: https://reviews.llvm.org/D109240


  Commit: e6c778f861ccb43064fb0e17790e3ee4fff4880f
      https://github.com/llvm/llvm-project/commit/e6c778f861ccb43064fb0e17790e3ee4fff4880f
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2022-10-24 (Mon, 24 Oct 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll

  Log Message:
  -----------
  GlobalISel: Artifact combine merge-like and unmerge into unmerge

Recognize when source could have been unmerged to pieces with DstTy
without having to split source to smaller elements
and then merge small elements into DstTy pieces.
This happens when vector was meant to be split to sub-vectors but there
was leftover. At this point artifact combiner have already dealt with
leftover and we can continue to use sub-vectors.

Differential Revision: https://reviews.llvm.org/D109241


  Commit: cbc378ecb87e3f31dd5aff91f2a621d500640412
      https://github.com/llvm/llvm-project/commit/cbc378ecb87e3f31dd5aff91f2a621d500640412
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2022-10-24 (Mon, 24 Oct 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

  Log Message:
  -----------
  GlobalISel: Artifact combine merge-like and unmerges into merge-like

Recognize when sub-vectors have been split to elements which are used to
build large vector.
This happens when instructions have different vector sizes available.
For example a few arithmetic instruction are required to process all
elements of larger vector that can be stored using one instruction.

Differential Revision: https://reviews.llvm.org/D109242


Compare: https://github.com/llvm/llvm-project/compare/8d995c085f96...cbc378ecb87e

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