[all-commits] [llvm/llvm-project] 82c6f1: [mlir] Better handling for bit groups in enum pars...

[River Riddle via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 82c6f10052ac57b8a51b97898f32b40ec806da03
      https://github.com/llvm/llvm-project/commit/82c6f10052ac57b8a51b97898f32b40ec806da03
  Author: River Riddle <riddleriver at gmail.com>
  Date:   2022-10-23 (Sun, 23 Oct 2022)

  Changed paths:
    M mlir/test/mlir-tblgen/enums-gen.td
    M mlir/tools/mlir-tblgen/EnumsGen.cpp

  Log Message:
  -----------
  [mlir] Better handling for bit groups in enum parser/printer

We currently wrap all multi-bit cases with a string, but this is
overly restrictive. This commit refactors to use keywords when
we know they are valid, and only degrade to string when the validity
of the bitgroup is unknown.

Differential Revision: https://reviews.llvm.org/D136540


  Commit: c8496d292e0ae4ba60b3905de884c83d66387e7e
      https://github.com/llvm/llvm-project/commit/c8496d292e0ae4ba60b3905de884c83d66387e7e
  Author: River Riddle <riddleriver at gmail.com>
  Date:   2022-10-23 (Sun, 23 Oct 2022)

  Changed paths:
    M flang/test/Fir/affine-promotion.fir
    M mlir/lib/IR/AsmPrinter.cpp
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
    M mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
    M mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d.mlir
    M mlir/test/Dialect/Affine/affine-data-copy.mlir
    M mlir/test/Dialect/Affine/affine-loop-normalize.mlir
    M mlir/test/Dialect/Affine/dma-generate.mlir
    M mlir/test/Dialect/Affine/loop-tiling-parametric.mlir
    M mlir/test/Dialect/Affine/loop-tiling-validity.mlir
    M mlir/test/Dialect/Affine/loop-tiling.mlir
    M mlir/test/Dialect/Affine/ops.mlir
    M mlir/test/Dialect/Affine/scalrep.mlir
    M mlir/test/Dialect/Affine/unroll-jam.mlir
    M mlir/test/Dialect/Affine/unroll.mlir
    M mlir/test/Dialect/Linalg/bubble-up-extract-slice-op.mlir
    M mlir/test/Dialect/Linalg/tile-to-foreach-thread.mlir
    M mlir/test/Dialect/MemRef/subview.mlir
    M mlir/test/Dialect/SCF/parallel-loop-specialization.mlir
    M mlir/test/Dialect/Vector/vector-transforms.mlir
    M mlir/test/IR/affine-map.mlir
    M mlir/test/IR/affine-set.mlir
    M mlir/test/IR/core-ops.mlir
    M mlir/test/IR/parser.mlir
    M mlir/test/IR/print-attr-type-aliases.mlir
    M mlir/test/Transforms/loop-fusion-2.mlir
    M mlir/test/Transforms/loop-fusion.mlir
    M mlir/test/Transforms/pipeline-data-transfer.mlir

  Log Message:
  -----------
  [mlir] Refactor alias generation to support nested aliases

We currently only support one level of aliases, which isn't great
in situations where an attribute/type can have multiple duplicated
components nested within it(e.g. debuginfo metadata). This commit
refactors alias generation to support nested aliases, which requires
changing alias grouping to take into account the depth of child
aliases, to ensure that attributes/types aren't printed before the
aliases they use.

The only real user facing change here was that we no longer print
0 as an alias suffix, which would be unnecessarily expensive to keep
in the new alias generation method (and isn't that valuable of a
behavior to preserve).

Differential Revision: https://reviews.llvm.org/D136541


  Commit: 3bef1e0f4c1d7fd901b58abe0c5c0e67da764ba2
      https://github.com/llvm/llvm-project/commit/3bef1e0f4c1d7fd901b58abe0c5c0e67da764ba2
  Author: River Riddle <riddleriver at gmail.com>
  Date:   2022-10-23 (Sun, 23 Oct 2022)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
    M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
    M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
    M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
    A mlir/test/Dialect/LLVMIR/debuginfo.mlir

  Log Message:
  -----------
  [mlir:LLVM] Add attribute/op definitions for debug info

This adds a subset of the necessary metadata for defining
debug info in the LLVM dialect. It doesn't import everything,
but just enough to start actually generating LLVM debug info
the expected way. Export/Import to LLVMIR will be added in a
followup.

Differential Revision: https://reviews.llvm.org/D136542


Compare: https://github.com/llvm/llvm-project/compare/38389f3109e8...3bef1e0f4c1d