[all-commits] [llvm/llvm-project] 2b32e4: [RISCV] Add basic support for the sifive-7-series ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b32e4f98b4f0e9e6a7c301b627ff75d9af8699e
      https://github.com/llvm/llvm-project/commit/2b32e4f98b4f0e9e6a7c301b627ff75d9af8699e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-17 (Mon, 17 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll

  Log Message:
  -----------
  [RISCV] Add basic support for the sifive-7-series short forward branch optimization.

sifive-7-series has macrofusion support to convert a branch over
a single instruction into a conditional instruction. This can be
an improvement if the branch is hard to predict.

This patch adds support for the most basic case, a branch over a
move instruction. This is implemented as a pseudo instruction so
we can hide the control flow until all code motion passes complete.

I've disabled a recent select optimization if this feature is enabled
in the subtarget.

Related gcc patch for the same optimization https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg211045.html

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135814