[all-commits] [llvm/llvm-project] 8055aa: [AArch64][GlobalISel] Make vector G_SEXT_INREG leg...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8055aa8e8a7780124bbf1c7bea90c17018c12d01
      https://github.com/llvm/llvm-project/commit/8055aa8e8a7780124bbf1c7bea90c17018c12d01
  Author: Amara Emerson <amara at apple.com>
  Date:   2022-10-05 (Wed, 05 Oct 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Make vector G_SEXT_INREG legal and allow combining.

As a result of making these legal, and tweaking the combine to allow vectors,
we generate vector G_SEXT_INREG during legalization.

The reason we want to make these legal in the first place is to allow for
more combine opportunities. Once those have been done, we can just lower them
back to shifts in the post-legalizer lowering.

This needs to be one commit otherwise we start causing tests to fail due to
incomplete support for selection etc.


  Commit: c5cebf78bdca35faa44b07fa4d3cb99bba7f2027
      https://github.com/llvm/llvm-project/commit/c5cebf78bdca35faa44b07fa4d3cb99bba7f2027
  Author: Amara Emerson <amara at apple.com>
  Date:   2022-10-05 (Wed, 05 Oct 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/min-max.ll
    M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

  Log Message:
  -----------
  [GlobalISel] Add computeNumSignBits() support for compares.

Doing so allows G_SEXT_INREG to be combined away for many vector cases.

Differential Revision: https://reviews.llvm.org/D135168


Compare: https://github.com/llvm/llvm-project/compare/43fe6f7cc35d...c5cebf78bdca