[all-commits] [llvm/llvm-project] cefb7a: [VP][RISCV] Add vp.copysign and RISC-V support.

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cefb7aab61e71b7ea7a298e5edff0abdf117bd9a
      https://github.com/llvm/llvm-project/commit/cefb7aab61e71b7ea7a298e5edff0abdf117bd9a
  Author: Yeting Kuo <yeting.kuo at sifive.com>
  Date:   2022-10-01 (Sat, 01 Oct 2022)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/IR/VPIntrinsics.def
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
    M llvm/unittests/IR/VPIntrinsicTest.cpp

  Log Message:
  -----------
  [VP][RISCV] Add vp.copysign and RISC-V support.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134935