[all-commits] [llvm/llvm-project] d7600c: [DAG] select Cond, C, -1 --> or (sext (not Cond)), ...

[deadalnix via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d7600c7ccb475dd57bbb857872455435d72fd280
      https://github.com/llvm/llvm-project/commit/d7600c7ccb475dd57bbb857872455435d72fd280
  Author: Amaury Séchet <deadalnix at gmail.com>
  Date:   2022-09-30 (Fri, 30 Sep 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/pr16031.ll
    M llvm/test/CodeGen/X86/select_const.ll
    M llvm/test/CodeGen/X86/zext-sext.ll

  Log Message:
  -----------
  [DAG] select Cond, C, -1 --> or (sext (not Cond)), C when C is MVT::i1

In the spirit of D130765 . Get rid of cbranches and/or cmov. Usually shorter, but sometime not, becaus eit's hard to prededict when dependency breaking xor will be introduced.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D134736