[all-commits] [llvm/llvm-project] ac7418: [mlir][sparse] Adding isSorted bit to SparseTensorCOO

[wren romano via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac741889c1448170f15a4f4bf93db6cc89518169
      https://github.com/llvm/llvm-project/commit/ac741889c1448170f15a4f4bf93db6cc89518169
  Author: wren romano <2998727+wrengr at users.noreply.github.com>
  Date:   2022-09-29 (Thu, 29 Sep 2022)

  Changed paths:
    M mlir/include/mlir/ExecutionEngine/SparseTensor/COO.h

  Log Message:
  -----------
  [mlir][sparse] Adding isSorted bit to SparseTensorCOO

This is a followup to the refactoring of D133462, D133830, D133831, and D133833.

Depends On D133833

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D133839